1. Field of the Invention
The present invention relates to a microcomputer including a plurality of clock generating sources built therein.
2. Description of the Prior Art
A typical microcomputer mounted in equipment includes a plurality of clock generating sources and selects one of them best suited to the use and operating condition of the microcomputer.
For example, a high-speed clock signal having a frequency in a MHz range is selected when the microcomputer is in a normal operating condition, whereas a low-speed clock signal having a frequency of 32 kHz is selected and a clock generating source for generating the high-speed clock is stopped to reduce the power consumption when the microcomputer is idle, that is, when it is in a sleep state.
Referring next to FIG. 7, it illustrates a block diagram showing the structure of such a prior art microcomputer. In the figure, reference numeral 1 denotes a central processing unit or CPU built in the microcomputer, numeral 2 denotes a bus for connecting the CPU 1 to a clock generating circuit 3 for generating a clock signal as a system clock, numeral 4 denotes register for storing a control value to control the oscillating state of a main-clock generating circuit 7, numeral 5 denotes register for storing a control value to control the oscillating state of a sub-clock generating circuit 8, and numeral 6 denotes a register for storing a control value to control a switch 9 so that the switch 9 switches between two destinations or two input terminals to connect one of them to its output terminal.
The main-clock generating circuit 7 generates a high-speed clock signal or main-clock signal having a frequency in a MHz range. The sub-clock generating circuit 8 generates a low-speed clock signal having a frequency lower than that of the high-speed clock signal generated by the main-clock generating circuit 7. The switch 9 selects either the high-speed clock signal from the main-clock generating circuit 7 applied thereto via the input terminal 9a thereof or the low-speed clock signal from the sub-clock generating circuit 8 applied thereto via the other input terminal 9b thereof, and then furnishes the selected clock signal, via the output terminal 9c, to the CPU 1 and so on in the microcomputer.
In operation, when there is a need to provide a high-speed operating condition, the CPU 1 stores a control value xe2x80x9c0xe2x80x9d in the register 4 and stores a control value xe2x80x9c1xe2x80x9d in the register 5 in order to use the high-speed clock signal generated by the main-clock generating circuit 7. The CPU 1 further stores a control value xe2x80x9c1xe2x80x9d in the register 6.
As a result, the main-clock generating circuit 7 starts generating the high-speed clock signal, whereas the sub-clock generating circuit 8 stops the generation of the low-speed clock signal. The switch 9 connects the output terminal 9c to the first input terminal 9a so as to furnish the high-speed clock signal generated by the main-clock generating circuit 7, as the system clock, to the CPU 1 and so on.
In contrast, when the CPU 1 keeps the sleep state, it writes control values into the registers 4 to 6 to select the low-speed clock signal generated by the sub-clock generating circuit 8 and stop the oscillation of the main-clock generating circuit 7 to reduce the power consumption. In this case, the CPU 1 stores a control value xe2x80x9c1xe2x80x9d in the register 4 and stores a control value xe2x80x9c0xe2x80x9d in the register 5 in order to use the low-speed clock signal generated by the sub-clock generating circuit 8. The CPU 1 further stores a control value xe2x80x9c0xe2x80x9d in the register 6.
As a result, the sub-clock generating circuit 8 starts generating the low-speed clock, whereas the main-clock generating circuit 7 stops the generation of the high-speed clock signal. The switch 9 connects the output terminal 9c to the second input terminal 9b so as to furnish the low-speed clock signal generated by the sub-clock generating circuit 8, as the system clock, to the CPU 1 and so on.
While a prior art microcomputer constructed as above can select a clock signal best suited to the use and operating condition of the microcomputer, it suffers from a problem that if the CPU 1 malfunctions and then stores a control value xe2x80x9c1xe2x80x9d in both the registers 4 and 5, both of the main-clock and sub-clock generating circuits 7 and 8 stop the generation of the high-speed and low-speed clocks and the system therefore comes to a deadlock. In this case, the deadlock is a state in which any operation other than power shutdown and resetting of the system cannot return the system to its original state. The deadlock in which the control process is locked and the system cannot be returned to its original state can thus be fatal to the equipment equipped with the microcomputer.
Japanese Patent Application Publication (TOKKAIHEI) No. 3-231319 discloses a method of allowing a selected clock generating source to neglect an instruction to stop generation of a clock signal, and to continue to generate the clock signal, in order to prevent the system from coming to a deadlock. In the prior art, since the CPU, however, cannot determine whether the CPU itself malfunctions, and therefore, cannot perform a recovery processing, such as eliminating the cause of the malfunction, there is a possibility that the system further falls into an abnormal condition if the CPU malfunctions.
The present invention is proposed to solve the above problem. It is therefore an object of the present invention to provide a microcomputer capable of causing a CPU to perform a recovery processing when the CPU malfunctions to provide an instruction to perform an unauthorized processing.
In accordance with one aspect of the present invention, there is provided a microcomputer comprising: a plurality of clock generating sources for generating a plurality of clock signals having different frequencies; a selecting unit for selecting one of the plurality of clock signals generated by the plurality of clock generating sources according to a selection instruction from a central processing unit or CPU; a clock generation stop unit, responsive to a stop instruction to stop generation of a clock signal other than the selected clock signal from the CPU, for causing a corresponding clock generating source to stop the generation of the clock signal; and an unauthorized stop process detecting unit, responsive to a stop instruction to stop the generation of the selected clock signal from the CPU, for determining that the CPU has provided an instruction to perform an unauthorized process of causing a selected clock generating source to stop the generation of the selected clock signal.
In accordance with a preferred embodiment of the present invention, when the unauthorized stop process detecting unit determines that the CPU has provided an instruction to perform an unauthorized process of causing a selected clock generating source to stop the generation of the selected clock signal, it furnishes an interruption signal to the CPU.
In accordance with another preferred embodiment of the present invention, when the unauthorized stop process detecting unit determines that the CPU has provided an instruction to perform an unauthorized process of causing a selected clock generating source to stop the generation of the selected clock signal, it resets the CPU.
In accordance with another preferred embodiment of the present invention, when the unauthorized stop process detecting unit determines that the CPU has provided an instruction to perform an unauthorized process of causing a selected clock generating source to stop the generation of the selected clock signal, it resets a system equipped with the microcomputer.
In accordance with another aspect of the present invention, there is provided a microcomputer comprising: a plurality of clock generating sources for generating a plurality of clock signals having different frequencies; a selecting unit for selecting one of the plurality of clock signals generated by the plurality of clock generating sources according to a selection instruction from a central processing unit or CPU; a clock generation stop unit, responsive to a stop instruction to stop generation of a clock signal other than the selected clock signal from the CPU, for causing a corresponding clock generating source to stop the generation of the clock signal; and a clock generation stop detecting unit for monitoring generation of the clock signal selected by the selecting unit, and for determining whether or not the generation of the selected clock signal is stopped.
In accordance with a preferred embodiment of the present invention, when the clock generation stop detecting unit determines that the generation of the selected clock signal is stopped, it furnishes an interruption signal to the CPU.
In accordance with another preferred embodiment of the present invention, when the clock generation stop detecting unit determines that the generation of the selected clock signal is stopped, it resets the CPU.
In accordance with another preferred embodiment of the present invention, when the clock generation stop detecting unit determines that the generation of the selected clock signal is stopped, it resets a system equipped with the microcomputer.